Stored program digital computer systems typically include an addressable central memory in which are stored instructions and operands used during data processing operations. Access to certain types of such central memories employs a protocol using an address input path carrying a signal encoding a central memory address. The address encoded thereon is transferred to the memory when a request signal is placed on a request line. The request signal causes the memory to accept the address and provide the word specified by the address as the output. Further, to deal with a situation where memory requests occur more rapidly than the memory can respond, one can employ address queue or pipeline circuitry in which each address accompanying a request signal may be temporarily stored until or while being answered.
Such digital computers also frequently employ high-speed buffer or cache memories in which both instructions and operands may be stored. In situations where several or frequent references are made to a particular instruction or operand, and the number of the references to the other instuction or operands between each reference to a particular one is not too great, a relatively small high-speed buffer memory can substantially increase the overall processing speed for two reasons. On the one hand, it is possible to reduce the number of references to the relatively slow central memory, and secondly, individual instructions and operands can be made available much more rapidly to the various sections of the computer
This invention is intended to operate mainly with a buffer memory intended to store instructions, although there is no theoretical reason why it cannot with modifications be applied to those storing operands as well.
When a central memory is used to store instructions and supply them to an instruction word buffer memory, it is convenient to provide with each instruction word central memory address supplied to the central memory, the instruction word buffer address specifying the instruction word buffer memory storage location at which the retrieved instruction word should be stored. As each of these central memory addresses are shifted along the address queue or pipeline, the instruction word buffer address is shifted with it and issued with the instruction word to identify the buffer memory location for storing the associated instruction word.
Further, in such computers, it is conventional that an instruction processor is provided to execute individual instruction words from the instruction word buffer memory. To provide continuity in instruction execution, each instruction word specifies in some way the central memory address of the next instruction word to be executed. A buffer addressing control receives each such central memory address specified and assigns an instruction word buffer address to the central memory address if one has not yet been assigned, or if an instruction word buffer address has already been assigned to the central memory address for the next instruction word buffer address, determines this buffer address assignment. Lastly, if the instruction word buffer memory is full and no prior assignment of central memory address to buffer address exists, the buffer addressing control selects an instruction word buffer address currently assigned to a central memory address and changes its assignment to the new central memory address.
Should the instruction word buffer contain a complete instruction loop which is executed repeatedly, execution can proceed very rapidly after the first time through because no central memory references for currently executed instruction words are needed. If during this time instructions likely to be executed after those currently being executed are requested from central memory, processing speed can be further increased. Such look-ahead apparatus is common in computers of this type. If the programs executed on such machines are properly designed, it is possible for their execution to occur with very little waiting for instructions to be requested from central memory, since the look-ahead apparatus has pre-fetched most instructions prior to their addresses being actually specified.
Further discussion of these and related considerations is present in the following references: U.S. Pat. Nos. 3,928,857; 4,110,822; 3,573,854; 3,736,567; and 3,699,535. In particular, U.S. Pat. No. 3,928,857 is deemed to be the art closest to the invention described below.